Particularly wafers including small chips, for example chips formed using a 65 nm technology (or even smaller), may include layers with a small dielectric constant, so-called low-k-layers. The low-k-layers may be rather brittle, for example more brittle than silicon dioxide or other typically used dielectrics. This may cause problems when the wafer is sawed for dicing it into individual chips. The individual chips may suffer from so-called chipping (small chips of material broken off at newly formed edges of the chips). The chipping may be so severe that the chips have to be discarded.
In order to avoid a functionality of the chips to suffer from the chipping, a separation between functional areas of the chips, in which the dicing may be performed, may be enlarged. However, this may decrease a number of chips per wafer and thereby increase manufacturing costs.
Alternatively, the brittle layers may be separated using a laser, e.g. by laser ablation (also referred to as laser grooving). However, both the ablated material (which may settle on the chips) and/or heat introduced by the laser into the wafer, e.g. into active regions of the chips, may cause damage to the chips, which may have to be discarded. This means that a yield of the production process may be reduced, thereby increasing manufacturing costs.